High-performance integrated circuits, particularly microprocessors, commonly provide various modes of operation. Microprocessors typically operate in one of various operating modes such as high performance, low power, standby, or test modes. Microprocessors operate in a high-performance mode when tasked with timing-critical applications. Some microprocessors use pulsed sequential storage elements, e.g., pulsed latches or flip-flops, to improve performance when executing instructions relating to timing-critical applications. For example, pulsed sequential storage elements are dispersed throughout instruction execution pipelines for improving data transfer speed between pipeline stages. Pulsed sequential storage elements capture and/or launch data in response to a pulse clock signal, i.e., a clock signal having a pulse width less than half of the clock period.
However, when configured in an operating mode that is timing insensitive, e.g., low power, standby or test modes. Particularly, the pulsed sequential storage elements contained in a microprocessor may not function properly. For example, during scan testing, pulsed sequential storage elements are commonly arranged in one or more “scan chains” to facilitate loading of test data into a microprocessor and unloading of test results from the microprocessor. When configured as scan chains, pulsed sequential storage elements commonly do not function properly when triggered by narrow clock pulses. As such, a phase clock signal, i.e., a clock signal having a pulse width approximately half of the clock period, is used to clock pulsed sequential storage elements to ensure proper functionality.
Conventional microprocessors commonly include separate clock generators for providing both pulse and phase clock signals to pulsed sequential storage elements. That is, one clock generator provides a pulse clock signal for clocking the pulsed storage elements during timing critical operating modes and a separate clock generator provides a phase clock signal for clocking the pulsed storage elements during timing insensitive operating modes. The clock signal outputs of the separate clock generators are presented to a multiplexer circuit for selection based on the particular operating mode of the microprocessor. In such applications, dual clock signal generators consume additional area and power. Further, a clock signal produced by one of the clock generators is subjected to additional capacitance associated with the inactive clock generator.
Clock skew further complicates the use of separate clock generators for providing both pulse and phase clock signals to pulsed sequential storage elements. Clock skew is a spatial variation of a clock signal as it is distributed through a system such as a microprocessor. Clock skew is commonly caused by various resistive/capacitive (RC) characteristics of the clock paths and different loading of the clock signal at different points in the microprocessor. Clock skew is reduced when the dual clock generators have similar clock input-to-output latency. In other words, clock generators that produce clock signals having approximately the same delay minimize clock skew. However, producing separate clock generators having similar clock input-to-output latency is difficult given various considerations such as fabrication and circuit layout variations.